1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of driving the semiconductor memory device. In particular, the present invention relates to a semiconductor memory device that is applicable to a cache and a method of driving the semiconductor memory device.
2. Description of the Related Art
Many central processing units (CPU) include a control circuit and a memory circuit called a cache memory in addition to an arithmetic unit. When a high-speed cache memory is provided in a central processing unit, the frequency of access to a low-speed main memory such as a dynamic random access memory (DRAM) provided outside the central processing unit can be reduced. As a result, the processing speed of the central processing unit can be increased.
A structure and a method of driving the cache memory are described with reference to an n-way set associative cache memory.
The n-way set associative cache memory includes n (n is a natural number) sets, n comparison circuits each comparing tags, and a selection circuit selecting data. Note that one set and one comparison circuit are paired. Each set includes a plurality of regions called lines. In order to specify each of the lines uniquely with a first bit column of an address of the main memory, a first bit column is assigned in advance to each of the lines. Therefore, the number of lines is less than or equal to m (m is a natural number of 2 or larger) that can be specified with the first bit column of the address of the main memory. Note that each line includes a tag field storing a second bit column of the address and a data field storing copy data of the main memory.
First, an example of a method of storing single data which is specified with the address in the n-way set associative cache memory is described. A control circuit of a central processing unit selects lines to each of which the first bit column of the address is assigned in advance in the respective sets with reference to the first bit column of the address of the single data so that the single data can be stored in the lines. That is, in the n-way set associative cache memory, n lines are selected in total for single data.
Next, the control circuit specifies the line in which the oldest data is stored among the n lines, and the single data is overwritten to this line. Specifically, the second bit column of the address is stored in the tag field, and copy data of the main memory is stored in the data field.
Next, an example of a method of extracting specific data from the n-way set associative cache memory is described. When an arithmetic unit requests specific data from the control circuit, the control circuit seeks the line in which the data is stored using the first bit column and the second bit column of the address for specifying the data.
Specifically, the control circuit selects the n lines to each of which the first bit column of the address for specifying the data is assigned in advance. Next, the second bit columns stored in the tag fields of the selected lines are compared with the second bit column of the address for specifying the data by the comparison circuits connected to the respective sets. In the case where these match each other (this case is referred to as cache hit), the selection circuit outputs data stored in the data field of the line with which a cache hit is obtained to the control circuit together with a cache hit signal. Note that in the case where the requested data is not found in the n lines (this case is referred to as cache miss), the selection circuit outputs a cache miss signal to the control circuit and the arithmetic processing unit of the central processing unit requests data from the main memory.
A transistor including an oxide semiconductor in a channel formation region has been known (Patent Document 1). Since an oxide semiconductor layer can be comparatively easily formed by a sputtering method or the like, the transistor including an oxide semiconductor in a channel formation region can be easily formed.